The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for retargeting multiple patterned integrated circuit device designs.
Optical lithography is a crucial step in semiconductor manufacturing. The basic principle of optical lithography is quite similar to that of chemistry-based photography. The images of the patterned photo-mask are projected through the high-precision optical system onto the wafer surface, which is coated with a layer of light-sensitive chemical compound, e.g. photo-resist. The patterns are then formed on the wafer surface after complex chemical reactions and follow-on manufacturing steps, such as development, post-exposure bake, and wet or dry etching.
Multiple patterning is a class of technologies developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to use two patterning steps to print a set of features. Double patterning is a sequence of two separate patterning steps using two different photomasks to achieve wafer level frequency doubling. This technique is commonly used for patterns in the same layer which have incompatible densities or pitches than those resolvable by single patterning. In one important case, the two patterning steps may each consist of alternate lines with twice the spatial pitch or half of the spatial frequency of the original layouts. This allows the decomposition of dense patterns into two sparser patterns which are easier to print.
Double pattern lithography (DPL) is an effective technique to improve resolution. DPL theoretically doubles resolution through pitch splitting such that effective pitch of the layout for each patterning step is halved. DPL involves two separate exposures and etch/freeze steps (litho-etch-litho-etch or litho-freeze-litho-etch). DPL is expected to be needed for 20 nm technology and is one of the best candidate solutions for scaling to 14 nm technology and beyond.
For one-dimensional patterns at minimum pitch, layout decomposition for double patterning is trivial. Decomposition is very complex for more complicated two-dimensional patterns. DPL layout decomposition solutions typically cast layout decomposition as a graph coloring problem where two features less than a certain minimum spacing must be assigned different colors. DPL decomposition is very challenging to implement at the full-chip level when stitch insertion is considered. A stitch insertion in a polygon during decomposition indicates that one part of the polygon will be printed in the first patterning step while the remaining part of the polygon will be printed using second patterning, with the two parts joining together at the stitch location. Stitches can help in removing some decomposition conflicts but they can potentially break a polygon into multiple pieces. Conflicts that cannot be removed with stitch insertion require layout modification (sometimes major), which can be very challenging and costly (increase layout area). As a result, considering all candidate stitch insertion locations during layout decomposition is crucial to take full advantage of stitching capability.